Wafer inspection systems help a semiconductor manufacturer increase and maintain integrated circuit (IC) chip yields by detecting defects that occur during the manufacturing process. One purpose of inspection systems is to monitor whether a manufacturing process meets specifications. The inspection system indicates the problem and/or the source of the problem if the manufacturing process is outside the scope of established norms, which the semiconductor manufacturer can then address.
Evolution of the semiconductor manufacturing industry is placing ever greater demands on yield management and, in particular, on metrology and inspection systems. Critical dimensions are shrinking while wafer size is increasing. Economics is driving the industry to decrease the time for achieving high-yield, high-value production. Thus, minimizing the total time from detecting a yield problem to fixing it determines the return-on-investment for a semiconductor manufacturer.
Defect detection is becoming increasingly challenging as the semiconductor industry shrinks designs, adds new materials, or constructs new structures to increase density of transistors or memory elements. Defects are becoming smaller, have lower optical contrast, or are in noisier optical surroundings. Tools have been developed to use shorter wavelengths to improve resolution and optical contrast, to include features to filter out noise (e.g., using particular apertures, algorithms, or feature vectors), or to have increased light intensity to improve the optical signal. Despite these efforts, the ability to detect such defects with traditional approaches has increasingly long time-to-market or is becoming prohibitively more expensive to develop.
Recent solutions have attempted to address these issues. These include new light sources or features to filter out noise. However, current methods have difficulty keeping pace with technological advances and gaps in detection occur. For some gap defects, there is no known optical solution and the only alternatives are large amount of time using a scanning electron microscope (SEM) or electronic tests (eTest). For example, eTest is disclosed in U.S. Pat. No. 6,714,031, which is incorporated by reference in its entirety. Tool improvement alone may be insufficient to address all gaps in the ability to detect such defects. Even if detection with an advanced tool design is possible, the tool performance may be unable to keep pace with advanced semiconductor designs. Therefore, changes in manufacturing processes may be needed.
Semiconductor manufacturers have developed alternate solutions to allow optical inspection tools to detect defects. Semiconductor manufacturers have introduced additional process steps to more easily detect challenging defects (especially if there are no better alternatives) despite the additional process control that is required. One example is called “decoration” where semiconductor manufacturers deposit or remove materials that have high optical contrast to amplify detection of low contrast defects. For example, a post-SiO2 chemical mechanical planarization (CMP) layer consists of glass on top of logic transistors. It can be difficult to detect any small micro scratches due to low optical contrast and the small size of the defect. The defect can be easier to detect when a defect is decorated by etching material away. Other examples of methods to decorate wafers have been developed. However, even these alternate solutions cannot detect all defects.
Decoration cannot detect all defects simply by depositing material or by removing material. SEMs can find some of these difficult-to-detect defects, but SEM images take a long time to acquire for all defects on a wafer and cannot provide wafer signatures used for root cause analysis. Processing for eTest is costly due to the large number of process steps required.
Therefore, improved methods of defect detection are needed.